Embodiments of the present disclosure relate to an architecture for random access memory (RAM) circuit configurations. For example, certain embodiments relate to a ferroelectric RAM (FRAM) read only memory (ROM) wordline architecture. A method for power-on reset of a memory can include powering on the memory. The method can also include reading a first flag in a first bit of a first configuration wordline of the memory, wherein the first configuration wordline is one of a plurality of redundant configuration wordlines. The method can further include reading, when the first flag indicates the first configuration wordline is valid, a predetermined number of bytes of the wordline. The method can additionally include configuring operations of the memory based on the predetermined number of bytes, when the first flag indicates the first configuration wordline is valid.

A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

A semiconductor memory device includes a first memory transistor, a first memory capacitor, and a control circuit connected to them. The first memory transistor includes a first gate electrode, a first semiconductor layer, and a first insulating film containing an insulating material. The first memory capacitor includes a first electrode, a second electrode, and a second insulating film containing the insulating material of the first insulating film. The control circuit is configured to perform a first program operation that supplies the first gate electrode with a first program voltage, a second program operation that supplies the first gate electrode with a second program voltage larger than the first program voltage, and a first read operation that supplies at least one of the first electrode or the second electrode with a voltage. The control circuit performs the first or the second program operation after performing the first read operation.

A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Embodiments of the present disclosure relate to an architecture for random access memory (RAM) circuit configurations. For example, certain embodiments relate to a ferroelectric RAM (FRAM) read only memory (ROM) wordline architecture. A method for power-on reset of a memory can include powering on the memory. The method can also include reading a first flag in a first bit of a first configuration wordline of the memory, wherein the first configuration wordline is one of a plurality of redundant configuration wordlines. The method can further include reading, when the first flag indicates the first configuration wordline is valid, a predetermined number of bytes of the wordline. The method can additionally include configuring operations of the memory based on the predetermined number of bytes, when the first flag indicates the first configuration wordline is valid.

According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.

According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.