Read-only (RO) data consisting of a physically unclonable function (PUF) pattern is written to a ferroelectric random-access memory (FRAM) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.