A content addressable memory based on a self-rectifying ferroelectric tunnel junction element comprises: a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction; a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.

A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

In various aspects, a method for operating a memory cell arrangement is provided, including: providing a set of supply voltages to one or more sets of memory cell drivers to write one or more memory cells of the memory cell arrangement; wherein providing the set of supply voltages includes: ramping a first supply voltage of the set of supply voltages to a first predefined output voltage level, and ramping a second supply voltage of the set of supply voltages to a second predefined output voltage level dependent upon the first supply voltage, the first predefined output voltage level and the second predefined output voltage level defining a first predefined ratio, wherein, during the ramping of the first supply voltage and of the second supply voltage, a first ratio of the first supply voltage to the second supply voltage is substantially equal to or less than the first predefined ratio.

Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

A power switch circuit and non-volatile memory device including the same are provided. The power switch circuit includes a multi-voltage providing circuit configured to receive a first voltage and a second voltage greater than the first voltage, output a third voltage corresponding to the first voltage to a first output terminal, and output a fourth voltage corresponding to the second voltage to a second output terminal. The power switch circuit also includes a leakage current prevention circuit configured to cut off a leakage current flowing through the multi-voltage providing circuit. The multi-voltage providing circuit includes a first inverter which is driven using the second voltage. The leakage current prevention circuit is configured to cut off the leakage current flowing through the first inverter in response to both the first voltage and the second voltage being provided to the multi-voltage providing circuit.

Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.