Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.

A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.