Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.

According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.