Memristive devices based on tunable Schottky barrier are provided. In one aspect, a method of forming a memristive device includes: forming a semiconductor layer on a bottom metal electrode, wherein the semiconductor layer has workfunction-modifying molecules embedded therein; and forming a top metal electrode on the semiconductor layer, wherein the top metal electrode forms a Schottky junction with the semiconductor layer, and wherein the workfunction-modifying molecules are configured to alter a workfunction of the top metal electrode. A memristive device and a method for operating a memristive device are also provided.

Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and an organic molecular layer disposed between the variable resistance layer and the second conductive layer and containing organic molecules. Each of the organic molecules includes a first fused polycyclic unit having a first HOMO level, a second fused polycyclic unit having a second HOMO level higher in energy than the first HOMO level, and a third fused polycyclic unit disposed between the first fused polycyclic unit and the second fused polycyclic unit. The third fused polycyclic unit has a third HOMO level higher in energy than the first HOMO level and the second HOMO level.

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

Disclosed herein are redox-active 6-oxoverdazyl polymers having structures (S1) and (S2) synthesized via ring-opening metathesis polymerization (ROMP) and their solution, bulk, and thin-film properties investigated. Detailed studies of the ROMP method employed confirmed that stable radical polymers with controlled molecular weights and narrow molecular weight distributions (<1.2) were produced. Thermal gravimetric analysis of a representative example of the title polymers demonstrated stability up to 190 C., while differential scanning calorimetry studies revealed a glass transition temperature of 152 C. An ultrathin memristor device was produced using these polymers, namely a 10 nm homogeneous thin film of poly-[1,5-diisopropyl-3-(cis-5-norbornene-exo-2,3-dicarboxiimide)-6-oxoverdazyl] (P6OV), a poly-radical with three tunable charge states per each radical monomer: positive, neutral and negative.

The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Disclosed is a multilevel nonvolatile resistive random-access memory device including a lower electrode, an upper electrode, and an insulation film interposed between the lower electrode and the upper electrode. Each of the lower electrode and the upper electrode includes a plate-shaped portion, and a patterned portion formed on the plate-shaped portion, and the patterned portion includes a protruding 3-dimensional prism structure pattern in which a plurality of prism-shaped structures is repeatedly arranged at a constant interval in a given direction. The patterned portion of the lower electrode and the patterned portion of the upper electrode are arranged to face each other, and a longitudinal direction of the prism-shaped structures of the lower electrode patterned portion and a longitudinal direction of the prism-shaped structures of the upper electrode patterned portion cross each other.

Disclosed is a multilevel nonvolatile resistive random-access memory device including a lower electrode, an upper electrode, and an insulation film interposed between the lower electrode and the upper electrode. Each of the lower electrode and the upper electrode includes a plate-shaped portion, and a patterned portion formed on the plate-shaped portion, and the patterned portion includes a protruding 3-dimensional prism structure pattern in which a plurality of prism-shaped structures is repeatedly arranged at a constant interval in a given direction. The patterned portion of the lower electrode and the patterned portion of the upper electrode are arranged to face each other, and a longitudinal direction of the prism-shaped structures of the lower electrode patterned portion and a longitudinal direction of the prism-shaped structures of the upper electrode patterned portion cross each other.

A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.