A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.

The disclosure is directed to a memory circuit, an electronic device, and a method for implementing a ternary weight for in-memory computing. According to an aspect of the disclosure, the memory circuit includes a first memory cell having a first resistor; a second memory cell having a second resistor, a write driver configured to set the first resistor to a first resistance value, a second write driver configured to set the second resistor to a second resistance value, a differential current sensing circuit configured to determine a differential current between the first memory cell and the second memory cell based on the first resistance value and the second resistance value, and a ternary weight detector configured to determine a ternary weight which is selected among a first ternary weight, a second ternary weight, and a third ternary weight based on the differential current.

A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control circuit to open the pair of pass gates in response to at least one of the sensed signals at the sense circuit changing logical state. The pair of pass gates are opened to disconnect the pair of differential bit lines from the sense circuit.

An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

Embodiments relate to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. Embodiments are directed to writing and reading memory cell pairs.

A semiconductor resistive random-access memory (ReRAM) device of an array including at least one ReRAM cell is provided. The ReRAM cell includes a word line; a select line; a first bit line; a second bit line having a polarity opposite of that of the first bit line; a first resistor having a first terminal and a second terminal, wherein the second terminal of the first resistor is connected to the first bit line; a second resistor having a first terminal and a second terminal, the second terminal of the second resistor is connected to the second bit line; and a transistor having a gate terminal, a source terminal and a drain terminal; the word line is connected to the gate terminal, the select line connected to the source terminal, and the drain terminal connected to the first terminal of the first resistor and the first terminal of the second resistor.

A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.