The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.

A differential sensing device includes two reference cells, four path selectors, and four sample circuits. The first path selector is coupled to a first sensing node, the second reference cell, and a first memory cell. The second path selector is coupled to a second sensing node, the first reference cell, and the first memory cell. The third path selector is coupled to a third sensing node, the first reference cell, and a second memory cell. The fourth path selector is coupled to a fourth sensing node, the second reference cell, and the second memory cell. During a sample operation, the first sample circuit samples a first cell current, the second sample circuit samples the first reference current, the third sample circuit samples a second cell current, and the fourth sample circuit samples the second reference current.

A memory array and its operation method are provided. The array includes plural sets of word lines; plural bit lines; and plural memory cell each arranged at intersection of the plural sets of word lines and the plural bit lines. Each memory cell has first and second conductive filament component and a switch circuit, and one ends of the first and the second conductive filament components are coupled to corresponding bit lines and the other ends thereof are coupled to the switch circuit. In the differential mode, read is performed based on the reading currents of the first and the second conductive filament components. In the single-ended mode, read is performed based on a reference current and a reading current of the first or the second conductive filament component that is formed successfully.

A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Systems, methods, and apparatus related to memory devices. In one approach, a differential read operation is performed on a memory cell pair. Bitlines or digit lines are used to select the memory cells. The read operation is performed in a subthreshold mode in which the memory cells of the pair do not threshold (e.g., do not switch or snap). A voltage on a wordline used to select the memory cell pair is ramped to increasing magnitudes of voltage while the bitline or digit line voltages are held fixed. One or more detectors are used to determine a difference in leakage currents of the two memory cells. A logic state is determined (e.g., using at least one detector) based on the difference in leakage currents. A feedback circuit reduces voltages applied to the bitlines or digit lines in order to avoid thresholding the cells. The voltage reduction by the feedback circuit is triggered when the reading of the memory cell pair is complete.

A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

The disclosure is directed to a memory circuit, an electronic device, and a method for implementing a ternary weight for in-memory computing. According to an aspect of the disclosure, the memory circuit includes a first memory cell having a first resistor; a second memory cell having a second resistor, a write driver configured to set the first resistor to a first resistance value, a second write driver configured to set the second resistor to a second resistance value, a differential current sensing circuit configured to determine a differential current between the first memory cell and the second memory cell based on the first resistance value and the second resistance value, and a ternary weight detector configured to determine a ternary weight which is selected among a first ternary weight, a second ternary weight, and a third ternary weight based on the differential current.

Examples disclosed herein relate to digital hash code generation. A digital hash code generating device comprising a plurality of variable conductance elements. Each variable conductance element is coupled to a selected row line and to a selected column line of a crossbar array. Each variable conductance element comprises a conductance from a stochastic distribution of conductance. A plurality of comparator elements and each comparator element is connected to a set of at least two column lines. The plurality of comparator elements generates a hash code in response to a vector input applied to the plurality of row lines of the crossbar array.

A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control circuit to open the pair of pass gates in response to at least one of the sensed signals at the sense circuit changing logical state. The pair of pass gates are opened to disconnect the pair of differential bit lines from the sense circuit.