A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V.sub.TH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.

A method for reading out a resistive memory cell comprising two electrodes that are spaced from each other by an ion-conducting resistive material was developed, the memory cells being transferrable from a stable state having a higher resistance value (high resistive state, HRS) to a stable state having a lower resistance value (low resistive state, LRS) when a write voltage is applied. A read voltage is applied as a read pulse for reading out, wherein the number of ions driven through the ion-conducting resistive material during the pulse is set by way of the level and duration of the pulse in such a way, proceeding from the HRS state, they suffice for forming an electrically conducting path through the ion-conducting resistive material at least until the onset of a flow of current through this path, and thus for the transition into a metastable VRS state (volatile resistance state) having a reduced resistance value and a predefined relaxation time for return into the HRS state, but not for transition into the LRS state. In this way, it is ensured that, in all eases, the memory cell once is again in the same state after the read-out as it was prior to the read-out. This allows in particular memory elements that are composed of an antiserial circuit composed of two memory cells to be read out non-destructively, without this diminishing the option of implementing large arrays composed of these memory elements.

Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V.sub.TH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped V.sub.TH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.

Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.