An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

Apparatuses, methods, and systems for sensing two memory cells to determine one data value are described herein. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two memory cells to determine one data value. One data value is determined by sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing the memory state of a second one of the two memory cells using a second sensing voltage in the sense window. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

The present invention provides a memory apparatus capable of causing a gradual resistance change for information processing in an analog manner to a synaptic element for implementing a neuromorphic system. To this end, the present invention provides a memory apparatus including: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects, in the writing step, one or more memory cells from among the plurality of memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies, in the reading step, a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.

The present invention also provides a method for determining a synaptic weight in a memory apparatus including a memory array including a plurality of memory cells capable of selectively storing logic states, bit lines and word lines connected to the plurality of memory cells, the method including: (a) selecting one or more memory cells from among the plurality of memory cells, and sequentially applying a writing voltage to write logic states therein; (b) applying a reading voltage to the one or more memory cells that has been selected to have the logic states written therein; and (c) determining, by the applied reading voltage, a synaptic weight through a sum of currents flowing through the one or more memory cells that has been selected to have the logic states written therein, wherein the selected one or more memory cells are recognized to operate as one synaptic element.

A circuit for reading a programmed resistive state of resistive elements of a resistive memory, wherein each resistive element may be programmed to be in a first or a second resistive state, wherein the circuit includes a current integrator suitable for integrating a difference in current between a reading current flowing through a first of the resistive elements and a reference current.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.