A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.

Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.

Technologies relating to using a slew rate controller to reduce disturbance in a crossbar array circuit are disclosed. An example crossbar array circuit includes: one or more bit lines; one or more word lines; one or more 1T1R cells connected between the bit lines and the word lines; one or more ADCs connected to the one or more bit lines; one or more DACs connected to the one or more word lines; one or more access controls connected to the one or more 1T1R cells and configured to select a 1T1R cell in the one or more 1T1R cells and to program the selected 1T1R cell; and a slew rate controller connected to the DACs, wherein the slew rate controller is configured to receive an input signal. The slew rate controller may be configured to transform a step function input signal into a slew rate input signal.

A phase change memory (PCM) device including a bottom electrode, a bottom heater over the bottom electrode, a bottom buffer layer over the bottom heater, a PCM region over the bottom buffer layer, a top buffer layer over the PCM region, a top heater over the top buffer layer, and a top electrode over the top heater.

Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.

The present disclosure relates to a method for reading memory cells, and may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.

Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.