A read-write circuit mainly includes a read circuit and a write circuit. The write circuit comprises: a first voltage selector and a first voltage follower circuit that is electrically connected to the memristor storage array. The read-write circuit further includes a second voltage selector and a second voltage follower circuit that is electrically connected to the memristor storage array. Voltage stable following during bipolar writing is selected through the foregoing selector. Meanwhile, the reading circuit is provided with a variable resistor to select an access mode. The actual read-out voltage and the output voltage passing through the reference resistor under the same read voltage are input into a differential amplifier to obtain read-out data.

A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.

Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.

A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control circuit to open the pair of pass gates in response to at least one of the sensed signals at the sense circuit changing logical state. The pair of pass gates are opened to disconnect the pair of differential bit lines from the sense circuit.

Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

A semiconductor resistive random-access memory (ReRAM) device of an array including at least one ReRAM cell is provided. The ReRAM cell includes a word line; a select line; a first bit line; a second bit line having a polarity opposite of that of the first bit line; a first resistor having a first terminal and a second terminal, wherein the second terminal of the first resistor is connected to the first bit line; a second resistor having a first terminal and a second terminal, the second terminal of the second resistor is connected to the second bit line; and a transistor having a gate terminal, a source terminal and a drain terminal; the word line is connected to the gate terminal, the select line connected to the source terminal, and the drain terminal connected to the first terminal of the first resistor and the first terminal of the second resistor.

The present disclosure relates to a method for reading memory cells, and may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an mxn array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.