Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

A magnetic memory devices including a memory cell array including magnetic memory cells, a voltage generator configured to generate a gate voltage, a row decoder including a word line driver, the word line driver configured to be driven by the gate voltage generated from the voltage generator, and the row decoder connected to the memory cell array through a word line, a column decoder connected to the memory cell array through a plurality of bit lines and a plurality of source lines, and a write driver configured to transfer a write voltage to a bit line selected, from among the plurality of bit lines, by the column decoder, the word line driver driven by the gate voltage generated from the voltage generator may be provided.

The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.

A program current pulse (e.g., reset or set pulse) for a cross-point memory cell can be generated with improved efficiency and effectiveness by controlling the voltage applied to a selection transistor near the memory cell to increase current through the memory cell. In one example, a method involves applying a first voltage to a gate of a selection transistor coupled between the memory cell and a first supply voltage and transitioning the first voltage applied to the gate of the selection transistor to a second voltage. The transition from the first voltage to the second voltage causes an increase of current through the memory cell due to a charge sharing event between capacitances at the terminals of the selection transistor. The current path through the memory cell can then be disabled to terminate the program current pulse.

Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state.

A neuromorphic device includes a plurality of first control lines, a plurality of second control lines and a matrix of resistive processing unit cells. Each resistive processing unit cell is electrically connected with one of the first control lines and one of the second control lines. A given resistive processing unit cell includes a first resistive device and a second resistive device. The first resistive device is a positively weighted resistive device and the second resistive device is a negatively weighted resistive device.

A resistive memory with a self-termination control function and a self-termination control method for a resistive memory are provided. At least one memory cell comprises a cell transistor and a resistive element. A termination switch coupled to a source line terminates a write operation according to a comparison result. The comparator compares a voltage of a source line node with a reference voltage to output the comparison result, wherein the source line node is between the at least one memory cell and the termination switch, and the voltage of the source line node responses to the resistance of the resistive element. The variable resistance circuit provides an effective resistance according to a target resistance of the resistive element and outputs a reference current. The reference voltage node is coupled to the variable resistance circuit and the comparator and receives the reference current to provide the reference voltage to the comparator.

A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.