A semiconductor device including a variable resistance device is provided. A variable resistance element according to one embodiment of the present disclosure includes: an ion-receiving layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion-receiving layer; a gate pattern connected to an outer sidewall of the ion supply layer; and a source pattern connected to one of the top or bottom of the ion-receiving layer, and a drain pattern connected to the other one of the top or bottom of the ion-receiving layer, wherein a resistance of the ion-receiving layer varies depending on an amount of ions supplied from the ion supply layer based on a voltage applied to the gate pattern.

The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.

A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory.

A magnetic memory devices including a memory cell array including magnetic memory cells, a voltage generator configured to generate a gate voltage, a row decoder including a word line driver, the word line driver configured to be driven by the gate voltage generated from the voltage generator, and the row decoder connected to the memory cell array through a word line, a column decoder connected to the memory cell array through a plurality of bit lines and a plurality of source lines, and a write driver configured to transfer a write voltage to a bit line selected, from among the plurality of bit lines, by the column decoder, the word line driver driven by the gate voltage generated from the voltage generator may be provided.