A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

A storage device that avoids unauthorized access attributable to a snapback when simultaneously accessing a plurality of memory cells includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction, and a plurality of memory cells at a position where any of the plurality of first wires and any of the plurality of second wires intersect each other. A first driving unit supplies a first voltage having any of a positive polarity and a negative polarity or a zero potential to each of the plurality of first wires. A second driving unit supplies a second voltage with a different polarity from the first voltage to any one of the plurality of second wires intersecting a first wire to which the first voltage is supplied and supplies a zero potential to a remainder of the plurality of second wires.

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.

Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’).

Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state may include applying a first pulse having a first polarity to the memory cell. The method may include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method may also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.

A resistive memory cell includes a P-well region, an isolation structure, an N-well region, a first gate structure, a second gate structure, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a word line, a bit line, a conductor line and a program line. The third N-type doped region, the fourth N-type doped region and the N-well region are collaboratively formed as an N-type merged region. The bit line is connected with the first N-type doped region. The word line is connected with a conductive layer of the first gate structure. The conductor line is connected with the second N-type doped region and a conductive layer of the second gate structure. The program line is connected with the N-type merged region.