A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

A memory system and operating method thereof are provided. The non-volatile memory array is configured to store data. The controller is coupled to the non-volatile memory array. The memory controller is configured to provide a special write operation to write the data in the non-volatile memory array before a board mount operation is applied, and provide a regular write operation to write the data in the non-volatile memory array after the board mount operation is applied. A read margin provided by the special write operation is larger than a read margin provided by the regular write operation.

A storage array programming method and device for a resistive random access memory (RAM) are proposed. The resistive RAM comprising a storage array, the storage array comprising a group of storage units to which data is to be written. The programming method comprises: reading the currently stored data in the group of storage units and comparing bit by bit the currently stored data with the data to be written to determine whether the currently stored data is consistent with the data to be written, and generating a data write state according to the determination result; determining the data write state, and by a set operation or a reset operation, writing the data to be written only to the storage units where the currently stored data is inconsistent with the data to be written; checking whether any storage unit having a write failure exists during the set operation or the reset operation; if so, then repeating the previous steps until the writing is completed. The programming method can avoid repetitive writing, thus not only reducing write interference with a unit to improve writing efficiency of the unit, but also reducing power consumption of writing.

First data can be received at a memory sub-system. An operating temperature of the memory sub-system can be identified. An adjusted read voltage level can be determined in response to the operating temperature satisfying a threshold criterion pertaining to a threshold temperature. A read operation can be performed at the memory sub-system based on the adjusted read voltage level to retrieve second data. The first data can be stored at the memory sub-system based on the second data that was retrieved from the read operation that is based on the adjusted read voltage level.

The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

In a semiconductor recording device, a writing time as long as in the case where the number of bits to be subjected to ‘0’ writing is large even in the case where the number of bits to be subjected to ‘0’ writing in page writing is small. A population counter that controls the number of ‘0’ bits is provided. In addition, a writing driver is divided into a plurality of sub-writing drivers. In this configuration, as many sub-writing drivers as possible are driven as long as the number of ‘0’ writing bits is equal to or smaller than the maximum number of bits that can be simultaneously written.

A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.