A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

Methods, systems, and devices for cleaning memory blocks using multiple types of write operations are described. A counter may be incremented each time a write command is received. In response to the counter reaching a threshold, the counter may be reset and a flag may be set. Each time a cleaning of a memory block is to take place, the flag may be checked. If the flag is set, the memory block may be cleaned using a second type of cleaning operation, such as one using a force write approach. Otherwise, the memory block may be cleaned using a first type of cleaning operation, such as one using a normal write approach. Once set, the flag may be reset after one or more memory blocks are cleaned using the second type of cleaning operation.

A method to adaptively and dynamically set a bias scheme of a crossbar array for a write operation includes: performing a read-before-write operation to determine a number of cells n to be written during a write operation; comparing n to a predetermined threshold value to determine an efficient bias scheme; setting at least one voltage regulator to provide a bias voltage according to the efficient bias scheme; and performing the write operation. A method to determine threshold value to determine an efficient bias scheme of a crossbar array and an energy efficient crossbar array device are also described.

An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

An operation method of a resistive memory device includes receiving write data and an address; determining whether the write data is in a first state or in a second state; applying a first pulse to a target memory cell corresponding to the address, among a plurality of memory cells, when the write data is in the first state; and selectively applying, when the write data is in the second state, a second pulse to the target memory cell according to a comparison result of the write data and pre-read data which is pre-stored data read from the target memory cell.

Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.