A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-κ switching layer disposed on the bottom electrode, and a top electrode disposed on the high-κ switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.

A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

A resistive memory device including: first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells connected to the first conductive lines and the second conductive lines, wherein the memory cells include: a first memory cell including a first resistive memory layer and a first heating electrode layer, the first heating electrode layer includes a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance; and a second memory cell including a second resistive memory layer and a second heating electrode layer, the second heating electrode layer includes a second contact surface in contact with the second resistive memory layer and the second contact surface has a second contact resistance different from the first contact resistance.

In some embodiments, the present disclosure relates a phase change random access memory device that includes a phase change material (PCM) layer disposed between bottom and top electrodes. A controller circuit is coupled to the bottom and top electrodes and is configured to perform a first reset operation by applying a signal at a first amplitude across the PCM layer for a first time period and decreasing the signal from the first amplitude to a second amplitude for a second time period; and to perform a second reset operation by applying the signal at a third amplitude across the PCM layer for a third time period and decreasing the signal from the third amplitude to a fourth amplitude for a fourth time period greater than the second time period. After the fourth time period, the PCM layer has a percent crystallinity greater than the PCM layer after the second time period.

A circuit according to the present application includes a diode or other non-linear device coupled to a heating element of a phase-change material (PCM) radio frequency (RF) switch. The diode or other non-linear device allows an amorphizing pulse or a crystallizing pulse to pass to a first terminal of the heating element. The diode or other non-linear device substantially prevents a pulse generator providing the amorphizing pulse or crystallizing pulse from interfering with RF signals at RF terminals of the PCM RF switch. In an array of PCM cells each including a diode or other non-linear device, the diode or other non-linear device substantially prevents sneak paths that would otherwise enable an amorphizing or crystallizing pulse intended for a heating element of a selected cell of the array to be provided to heating elements of unselected cells of the array.

A memory device includes a plurality of memory cells, each memory cell including a switching element and a data storage element having a phase change material, and each memory cell connected to one of a plurality of wordlines and to one of a plurality of bitlines, a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell, and a programming circuit configured to input a program current to the selected memory cell to perform a program operation, to detect a holding voltage of the selected memory cell, and to adjust a magnitude of the program current based on the detected holding voltage. The selected memory cell is turned off when a voltage across the selected memory cell is lower than the holding voltage.

A method for fabricating a semiconductor device includes forming first contacts to a heater for programming, and forming second contacts to a phase-change material layer for resistance readout. The phase-change material layer is formed in proximity to the heater, and the first contacts are electrically isolated from the second contacts to provide separate programming and resistance readout control.