Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

An array includes a shared pulse generator and a plurality of cells. A selected cell the plurality of cells includes a phase-change material (PCM) and a heating element, the heating element being transverse to the PCM. The array further includes a row selector configured to connect the shared pulse generator to the selected cell, and a selector configured to connect the selected cell to a ground. The shared pulse generator provides an electrical pulse to cause the heating element in the selected cell to generate a heat pulse. In one approach, the selected cell also includes a non-linear device such as a diode, and the shared pulse generator provides the electrical pulse to a PCM RF switch of the selected cell through the non-linear device to change a state of the PCM RF switch.

A resistive element array circuit includes word lines, bit lines, resistive elements, a selector, a differential amplifier, and a ground terminal. The word lines are coupled to a power supply. The resistive elements are each disposed at an intersection of corresponding one of the word lines and corresponding one of the bit lines. The selector is configured to select one word line and one bit line. The differential amplifier includes a positive input terminal configured to be coupled to the selected one of the bit lines which is selected by the selector, a negative input terminal configured to be coupled to non-selected one of the bit lines which is not selected by the selector and to non-selected one of the word lines which is not selected by the selector, an output terminal being coupled to the negative input terminal. The ground terminal is coupled to the positive input terminal.

A resistive memory device including: first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells connected to the first conductive lines and the second conductive lines, wherein the memory cells include: a first memory cell including a first resistive memory layer and a first heating electrode layer, the first heating electrode layer includes a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance; and a second memory cell including a second resistive memory layer and a second heating electrode layer, the second heating electrode layer includes a second contact surface in contact with the second resistive memory layer and the second contact surface has a second contact resistance different from the first contact resistance.

An array includes a shared pulse generator and a plurality of cells. A selected cell the plurality of cells includes a phase-change material (PCM) and a heating element, the heating element being transverse to the PCM. The array further includes a row selector configured to connect the shared pulse generator to the selected cell, and a column selector configured to connect the selected cell to a ground. The shared pulse generator provides an electrical pulse to cause the heating element in the selected cell to generate a heat pulse. In one approach, the selected cell also includes a non-linear device such as a diode, and the shared pulse generator provides the electrical pulse to a PCM RF switch of the selected cell through the non-linear device to change a state of the PCM RF switch.

A circuit according to the present application includes a diode or other non-linear device coupled to a heating element of a phase-change material (PCM) radio frequency (RF) switch. The diode or other non-linear device allows an amorphizing pulse or a crystallizing pulse to pass to a first terminal of the heating element. The diode or other non-linear device substantially prevents a pulse generator providing the amorphizing pulse or crystallizing pulse from interfering with RF signals at RF terminals of the PCM RF switch. In an array of PCM cells each including a diode or other non-linear device, the diode or other non-linear device substantially prevents sneak paths that would otherwise enable an amorphizing or crystallizing pulse intended for a heating element of a selected cell of the array to be provided to heating elements of unselected cells of the array.

Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.