A variable resistance nonvolatile storage device includes: a variable resistance element having a state reversibly changeable between a high resistance state and a low resistance state; and a current supply circuit that supplies the variable resistance element with a low-resistance changing current for changing the state from the high resistance state to the low resistance state. The low-resistance changing current has a waveform that includes a first period and a second period along a time axis, the second period being subsequent to the first period. The current supply circuit applies to the variable resistance element: a first current during the first period; and a second current during the second period, the second current being smaller than the first current. The first current is not zero at an end of the first period, and the second current is not zero at a start of the second period.

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Methods, systems, and devices for cleaning memory blocks using multiple types of write operations are described. A counter may be incremented each time a write command is received. In response to the counter reaching a threshold, the counter may be reset and a flag may be set. Each time a cleaning of a memory block is to take place, the flag may be checked. If the flag is set, the memory block may be cleaned using a second type of cleaning operation, such as one using a force write approach. Otherwise, the memory block may be cleaned using a first type of cleaning operation, such as one using a normal write approach. Once set, the flag may be reset after one or more memory blocks are cleaned using the second type of cleaning operation.

A memory includes first and second lines. A cell-array comprises memory cells located to intersection regions between the first and second lines. A controller applies a voltage to the memory cells via the first and second lines. The cell-array comprises a first area used for reading or writing of data in a normal operation, and a second area storing predetermined data used for adjustment of the controller. The controller writes first logical data into the first area by applying a first voltage thereto and writes second logical data by applying a second voltage smaller than the first voltage, in the normal operation. The controller applies a third voltage to both first cells storing the first logical data and second cells storing the second logical data in the second area and then reads the predetermined data, after power-on and before starting the normal operation.

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NH.sub.3 gases. The dry chemical gas removal process utilizing HF and NH.sub.3 gases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.

In a method for using or forming a semiconductor structure. The semiconductor structure may include a resistive random access memory (RRAM) gate with a first electrode and a second electrode. The RRAM gate may also include a switching layer that includes a dielectric material having a switching layer k-value and a switching layer thermal conductivity. The RRAM gate may also include a complimentary switching (CS) mitigation layer with a material having a CS k-value that is lower than the switching layer k-value and a CS thermal conductivity that is higher than the switching layer thermal conductivity.

A two-terminal atom-based switching device having a fast operating speed and high durability and a manufacturing method thereof are disclosed. It is possible to reduce a forming voltage during positive voltage forming by forming an oxygen vacancy percolation path through negative voltage forming, which is first forming, and forming high binding energy and low formation energy between oxygen vacancies and metal ions implanted through positive voltage forming which is second forming after the negative voltage forming. Further, since a significant amount of metal ions implanted into the insulating layer through negative voltage application switching after the positive voltage forming is removed, the volatility of the two-terminal atom-based switching device may be improved, and a stuck-on failure phenomenon in the durability may be prevented.

The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

In various embodiments. an electronic circuit is provided. The electronic circuit may include at least one memory cell and a control circuit configured to determine a formation state of the at least one memory cell and set a predefined function to a predefined state of executability (e.g., enabled or disabled) based on the determined formation states. For example, the predefined function may be set to the predefined state of executability only if the determined formation states of two or more memory cells match a predefined formation state pattern, or only if a minimum number or fraction of two or memory cells are in a predefined formation state. The formation state is either unformed or formed, wherein the unformed state is an electrically isolated state, and the formed state is a state into which an initially unformed memory cell is transformable and in which the formed memory cell is repeatedly switchable between a state of low electrical resistivity and a state of high electrical resistivity.