In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.

A storage device includes a resistance change memory element including a first electrode, a second electrode, a resistance change layer between the first and second electrodes, including at least two elements selected from a group consisting of germanium (Ge), antimony (Sb), and tellurium (Te), and having a crystal structure with a c-axis oriented in a first direction from the first electrode toward the second electrode, and a first layer between the first electrode and the resistance change layer and including nitrogen (N) and at least one of silicon (Si) or germanium (Ge).

Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.

A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.

A programmable logic device according to an embodiment includes: a plurality of first and second wiring lines; a plurality of resistive change elements each including a first electrode containing Ni and connected to corresponding one of the first wiring lines, a second electrode containing TiN and connected to corresponding one of the second wiring lines, a resistive change layer containing a hafnium oxide and arranged between the first electrode and the second electrode, and an insulation layer arranged between the resistive change layer and the second electrode, the insulation layer including at least one of an aluminum oxide, an iron oxide, a titanium oxide, a copper oxide, a nickel oxide, a tantalum oxide, a tungsten oxide, a chromium oxide, a rhenium oxide, and a hafnium oxynitride.

A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.

The present invention relates to resistive random access memory (ReRAM). Disclosed are a ReRAM and write operation method thereof. The write operation method comprises monitoring, under a pre-operation signal bias, whether a conversion from a high resistance stage (HRS)/low resistance stage (LRS) to a LRS/HRS begins to occur, and controlling a change in a conversion operation signal, thus conducting a setting/resetting operation. The write operation method improves the storage performance of the ReRAM.

A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.