Patent classifications
G11C2013/0085
Memory device, operating and control method thereof
A method of operating a memory device including a plurality of memory cells is provided. The method includes receiving a first write command, determining whether a target memory cell is deteriorated or not, in response to the first write command, and writing the second data by selectively erasing the target memory cell according to a result of the determination and by programming the target memory cell.
Apparatuses and methods for providing set and reset voltages at the same time
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.
MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a first program operation to the first one half page of a selected page with the first partial data; and performing a second program operation to the second one half page of the selected page with the second partial data. The first and second partial data may be programmed in the same first column region in the first and second one half pages, respectively.
System for writing data in a memory
A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.