A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2.sup.(N-M) th memory state; when the program verification of the 2.sup.(N-M) th memory state is passed, identifiers corresponding to the 1st to 2.sup.(N-M) th memory states stored by the main latch are made different from those corresponding to the 2.sup.(N-M)+1st to 2.sup.N th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N−2).

A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

A storage device performs a read operation, based on a temperature measured in a program operation or an erase operation. The storage device includes: a memory device including a plurality of memory blocks, the memory device measuring a temperature in a program operation or an erase operation; and a memory controller for setting an area in which the measured temperature is to be stored in the memory device, and controlling a read operation to be performed in the memory device. When a read command for a selected page among a plurality of pages included in each of the plurality of memory blocks is received from the memory controller, the memory device determines a read voltage and a pass voltage based on a temperature corresponding to the selected page and performs a read operation on the selected page by using the read voltage and the pass voltage.

A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.

Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.