Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.

Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.

Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state. The sequence of determining data values includes sensing the memory state of the first and the second MLCs using higher sensing voltages than the first and the second sensing voltages in subsequent sensing windows, in repeated iterations, until the state of the first and the second MLCs are determined. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state. The sequence of determining data values includes sensing the memory state of the first and the second MLCs using higher sensing voltages than the first and the second sensing voltages in subsequent sensing windows, in repeated iterations, until the state of the first and the second MLCs are determined. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.

In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.