A nonvolatile memory device includes: a plurality of word lines that are stacked; a pillar structure that penetrates through the word lines in a vertical direction; and a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure. The pillar structure includes: a vertical channel region disposed in a core; and a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.

A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer 2. N is an integer M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.

A nonvolatile memory device includes: a plurality of word lines that are stacked; a pillar structure that penetrates through the word lines in a vertical direction; and a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure. The pillar structure includes: a vertical channel region disposed in a core; and a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.

A nonvolatile memory device includes: a plurality of word lines that are stacked; a pillar structure that penetrates through the word lines in a vertical direction; and a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure. The pillar structure includes: a vertical channel region disposed in a core; and a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.