Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.

According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.

Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

An input/output circuit for a memory and a method of controlling the same are disclosed. The input/output circuit and the method of controlling the same are configured to prevent a memory element from being falsely or incorrectly programmed due to an ESD pulse. More particularly, the input/output circuit and the method of controlling the same include an ESD detection unit configured to detect a programming voltage or an ESD pulse on a pad terminal, a control logic unit configured to transmit a first voltage or a second voltage according to the programming voltage and the ESD pulse, and a switch unit configured to perform a turn-on or turn-off operation according to the first voltage or the second voltage.

A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.

A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0.sup.th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).