A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to detect an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to manage execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.

A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.

Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

A semiconductor package includes an external power supply node, a current monitoring node, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies includes a first circuit and a second circuit. The first circuit is configured to supply a first operating current to that semiconductor die from the external power supply node. The second circuit is configured to measure the first operating current and output the measured first operating current to the current monitoring node. The measured first operating current from each semiconductor die of the plurality of semiconductor dies is summed on the current monitoring node.

A semiconductor apparatus including a sudden power detection circuit, a power-on reset circuit, and a driving circuit. The sudden power detection circuit configured to detect an external power supply voltage and generate a sudden power detection signal. The power-on reset circuit configured to detect the voltage level of the external power supply voltage according to a reset reference voltage and generate a power-on reset signal. The driving circuit configured to perform a sudden power-off operation and a power-on reset operation.

The present invention detects a battery abnormality during a driving cycle or self-shutdown even when a battery voltage sensor is not mounted. In the present invention, a first storage region is provided with a failure information storage region and a second storage region management information storage region, a second storage region is provided with a failure information storage region and a first storage region management information storage region, and a management information access flag storage region for storing access information indicating a presence or absence of an access to management information of the first storage region and management information of the second storage region is provided separately from the first storage region and the second storage region.

A safekeeping device includes a case configured to house a storage device including a nonvolatile memory, and a processor configured to control electric power so that the electric power is supplied to the nonvolatile memory at a predetermined timing.

There are provided a microcontroller, a memory system having the same, and a method for operating the same. A memory system includes: a semiconductor memory performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and a controller for determining whether an error exists in the ROM data, using the status output signal.

A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane driver circuits and detect an occurrence of a quiet event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a high noise event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the high noise event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to determine whether the first independent plane driver circuit has a higher priority than the second independent plane driver circuit. Responsive to determining that the first independent plane driver circuit has a higher priority than the second independent plane driver circuit, the control logic is to suspend the high noise event associated with the second independent plane driver circuit and permitting the quiet event associated with the first independent plane driver circuit to occur.