The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2 ; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

A memory system in an embodiment includes: a nonvolatile memory; a memory controller configured to control the memory; and a power supply circuit configured to supply a voltage of power of at least one of the memory and the memory controller, wherein the power supply circuit is configured to: store first information having a value of the voltage to be supplied; output an output voltage based on the value of the voltage specified by the stored first information; detect an output current at an output end of the output voltage; compare a value of the detected output current with a threshold value; and update the stored first information to second information based on a result of the comparison, the second information having an updated value of the voltage to be supplied.

A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

Methods, systems, and devices for current budget adaption are described. A controller may be coupled with a set of memory devices. The controller may receive current consumption information from the set of memory devices and update a current consumption budget for the set of memory devices based on the current consumption information.

Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.

A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.

A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

A scheme for non-parametric optimal read threshold estimation of a memory system. The memory system includes a memory device including pages and a controller including a neural network. The controller performs read operations on a selected page using a read threshold set; obtain the read threshold set, a checksum value and an asymmetric ratio of ones count and zeros count which are associated with decoding of the selected page according to each of the read operations; provide the obtained read threshold set, the checksum value and the asymmetric ratio as input information to the neural network; and estimate, by the neural network, an optimal read threshold voltage based on the input information and weights including a combination of multiple matrices and bias vectors.