According to one embodiment, a cache memory system includes a cache memory and a cache controller. The cache memory can store first data to be read or written by a processor. The cache controller is configured to execute a refresh. The refresh includes reading the first data stored in the cache memory and writing the read first data to the cache memory. When executing the refresh, the cache controller is configured to exchange the first data stored in a first area of the cache memory for second data stored in a second area of the cache memory.

A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.

A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks, each block having a plurality of pages, each page having a plurality of memory cells, wherein the plurality of memory block includes an SLC (Single Level Cell) block and an MLC (Multi-Level Cell) block; and a controller suitable for programming input data transmitted from a host to both the SLC block and the MLC block in response to a first program command, and invalidating the input data programmed in the SLC block at a time point when the program operation for the MLC block is completed, when the memory system is powered on after an SPO (Sudden Power-Off) occurred while the program operation was performed on both the SLC block and the MLC block, the controller may perform a recovery operation to the MLC block based on valid data programmed in the SLC block.

A memory system includes: a semiconductor storage device including a memory cell array that includes memory cells and a temperature counter configured to increase a count value thereof at a rate that depends on a temperature of the memory cell array; and a memory controller configured to acquire the count value from the semiconductor storage device and reserve a refresh operation for a written memory cell of the memory cell array when a cumulative value of the count value, which is accumulated from when data was written to the memory cell to when the count value is acquired, exceeds a predetermined value.

A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.

An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. During a refresh operation, at least one of word lines is selected and a voltage of the channel semiconductor layer of the selected word line is returned to a voltage in a state in which a page is written by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer.