Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

A data storage device including, in one implementation, a non-volatile memory device having a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. The controller is configured to monitor a temperature of the data storage device and determine whether the monitored temperature exceeds a first temperature threshold. The controller is also configured to perform a default thermal throttling operation based on the monitored temperature exceeding the first temperature threshold, determine whether the monitored temperature exceeds a second temperature threshold, and perform a customized thermal throttling operation based on the monitored temperature exceeding the second temperature threshold.

A storage device includes a nonvolatile memory device that includes a first storage area and a second storage area. A controller of the storage device controls the nonvolatile memory device and performs a read reclaim operation of reading data stored in the first storage area of the nonvolatile memory device and writing the read data in the second storage area. In the read reclaim operation, the controller is further configured to allow the nonvolatile memory device to perform sample read operations on the first storage area and to determine locations of the second storage area, at which the data are to be written, based on results of the sample read operations.

Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.

Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

A request is received to perform a multi-plane operation for data residing on a first plane and a second plane of a memory device. A first set of trim values is obtained from a first set of registers of the memory device. The first set of trim values corresponds to a first voltage shift for the data at the first plane. A second set of trim values is obtained from a second set of registers of the memory device. The second set of trim values corresponds to a second voltage shift for the data at the second set of trim values for the data at the second plane. The multi-plane operation is performed using at least the first set of trim values for the data at the first plane and at least the second set of trim values for the data at the second plane.

Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.

A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.