G11C16/3418

Memory control method, memory storage device, and memory control circuit unit

A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.

Temperature and inter-pulse delay factors for media management operations at a memory device

An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

Data storage device and operating method thereof
11488648 · 2022-11-01 · ·

A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR DETECTING LEAKAGE STATE
20220351802 · 2022-11-03 ·

A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line; a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line; at least one word line leakage detection circuit, configured to detect a leakage state of the selected word line; and at least one coupling circuit corresponding to the word line leakage detection circuit. The coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit, and the isolation capacitor is used for isolating the word line leakage detection circuit and the word line driving circuit.

PROXIMITY DISTURB REMEDIATION BASED ON A NUMBER OF PROGRAMMED MEMORY CELLS
20220351788 · 2022-11-03 ·

A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.

MEMORY SUB-SYSTEM REFRESH
20220350521 · 2022-11-03 ·

A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

NAND temperature data management

Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

STORING HIGHLY READ DATA AT LOW IMPACT READ DISTURB PAGES OF A MEMORY DEVICE

A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

Write operations to mitigate write disturb

A first write operation is performed to write a first portion of a set of host data to a first location of a memory device. It is determined whether a first elapsed time since the first operation is performed does not satisfy a time condition. Responsive to determining that the first elapsed time does not satisfy the time condition, a second write operation is performed to write a second portion of the set of host data to a second location of the memory device not adjacent to the first location.

MEMORY SUB-SYSTEM SCAN

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.