A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

The present disclosure provides a shift register, including: an input circuit, electrically connected to a triggering signal line that provides a triggering signal, a first clock signal line that provides a first clock signal, and a first node; configured for controlling whether the triggering signal is outputted to the first node based on the first clock signal; a control circuit, electrically connected to the first node, a second node, the first clock signal line, a second clock signal line that provides a second clock signal, and a turn-on signal line that provides a turn-on signal, configured for controlling whether the turn-on signal is outputted to the second node; and an output circuit, electrically connected to the first node, the second node, a first signal line that provides a first signal, a second signal line that provides a second signal, and a driving signal output line that outputs a driving signal.

A precharging circuit, a scanning driving circuit, an array substrate, and a display device are provided. The precharging circuit includes an input end, an output end, and further includes a switching unit, first pull-up unit, and second pull-up unit. The switching unit has first end connected to first node; second end connected to the input end, and third end connected to second node, and is used for conducting the second end and the third end when first end is at high level; first pull-up unit has first end connected to the output end and second end connected to first node, and is used for pulling up potential of second end when first end is at high level; second pull-up unit has first end connected to second node and second end connected to output end, is used for pulling up potential of second end when first end is at high level.

A signal generating unit, a shift register, a display device and a signal generating method. The signal generating unit includes: a first output transistor; a second output transistor; a first-node potential control module, configured to output a first control signal to a gate electrode of the first output transistor under control of an inputted start signal; a second-node potential control module configured to output a second control signal, which has an opposite phase with the first control signal, to a gate electrode of the second output transistor; and a first capacitor structure configured to be charged when the first-node potential control module outputs a single-pulse-width level signal for controlling the first output transistor to be switched on, and to maintain the gate electrode of the first output transistor in an on state during a subsequent time period having one pulse width.

The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit.

Provided are an organic light-emitting diode (OLED) display and method of driving the same. An OLED display includes: a display panel including a plurality of pixels, each pixel including an OLED, an emission timing of each pixel being controlled in response to an EM signal, a shift register configured to generate an anti-phase EM signal based on gate shift clocks, and an inverter configured to: invert a phase of the anti-phase EM signal based on emission shift clocks, and generate the EM signal, wherein a driving frequency of the shift register and a driving frequency of the inverter are lower in a low-speed driving mode than in a normal driving mode, and wherein in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.

Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module having a first end connected to a second control signal end and a second end connected to the pull-up node, and being configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when output end is reset, the speed of resetting the output end can be increased.

A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

The present disclosure provides a shift register unit and a shift register, a gate driver circuit and a display apparatus where the shift register unit can be applied. A signal amplification module including two transistors each having a small channel width is added at an output node of the shift register unit. In this way, the output capability can be improved significantly with the same design parameters in case of a high load.

A signal generating unit, a shift register, a display device and a signal generating method. The signal generating unit includes: a first output transistor; a second output transistor; a first-node potential control module, configured to output a first control signal to a gate electrode of the first output transistor under control of an inputted start signal; a second-node potential control module configured to output a second control signal, which has an opposite phase with the first control signal, to a gate electrode of the second output transistor; and a first capacitor structure configured to be charged when the first-node potential control module outputs a single-pulse-width level signal for controlling the first output transistor to be switched on, and to maintain the gate electrode of the first output transistor in an on state during a subsequent time period having one pulse width.