Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types, each block of the set of blocks including pages of memory of a physical memory device, identifying subset of the pages of the block. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

Devices, systems and methods for improving performance of a memory device are described. An example method includes receiving one or more parameters associated with a plurality of previous read operations on a page of the memory device, wherein the previous read operations are based on a plurality of read voltages, determining, using the one or more parameters as an input to a deep neural network comprising a plurality of layers, an updated plurality of read voltages, wherein each of the plurality of layers is a fully connected layer, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device, wherein the deep neural network uses a plurality of weights that have been processed using at least one of (a) a pruning operation, (b) a non-uniform quantization operation, or (c) a Huffman encoding operation.

Example embodiments provide for a storage device that includes a storage controller including a plurality of analog circuits and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, reads the compensation data set from the first region of the at least one nonvolatile memory device, stores the read compensation data set therein, and adjusts the offsets of the plurality of analog circuits based on the stored compensation data set.

A static random-access memory and a fault detection circuit thereof are provided. The fault detection circuit includes: a bit line coupling circuit, coupled between a first bit line and a second bit line, wherein the bit line coupling circuit is adapted to use a bit line with a lower potential between the first bit line and the second bit line to couple a bit line with a higher potential between the first bit line and the second bit line to a floating low potential in response to performing the data write operation on the memory cell in a test mode by the write circuit; and a fault determining circuit, adapted to, in response to the memory cell being at the test mode, obtain and compare write data and read data corresponding to the write data, to determine whether the SRAM has a Data Retention Fault based on a comparison result.

A memory device configured to select a page having a probability that uncorrectable error correction codes (UECC) will occur by comparing a reference current with a sensing current, and configured to perform a read claim operation or an additional pulse applying operation on the corresponding page according to the comparison.

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.

Methods, systems, and devices supporting an auto-power on mode for biased testing of a power management integrated circuit (PMIC) are described. A system may program a PMIC of a memory system to a specific mode. The mode may cause the PMIC to apply a bias to a memory device of the memory system upon receiving power and independent of a command to apply the bias to the memory device. The system may transmit power to the memory system while controlling one or more operating conditions (e.g., temperature, humidity) for a threshold time. The PMIC may apply a bias to the memory device during the threshold time based on the PMIC being programmed to the mode and the transmitted power. The system may identify a capability or defect of the memory device resulting from transmitting the power to the memory system while controlling the operating conditions for the threshold time.

A corresponding value of a data state metric associated with each of a value of a plurality of values of a memory access operation parameter used in one or more memory access operation is measured. An optimal metric value based on the measured values of the predetermined data state metric is determined. An optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter is selected.