The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.

A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration code may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real address area.

A method for testing a memory chip includes: in response to read command for the memory chip, controlling clock signal to be kept in first state within first preset time period and at the same time controlling complementary clock signal to be kept in second state within first preset time period; in response to clock signal kept in the first state and complementary clock signal kept in the second state, keeping data strobe signal in the first state within second preset time period and at the same time keeping complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal and the complementary data strobe signal are kept in first and second states respectively, controlling first and second driving modules connected respectively to data strobe terminal and complementary data strobe terminal to operate and measure first and second resistance values respectively.

The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

A method for read reference voltage calibration of a non-volatile memory, NVM, such as flash memory, particularly of the NAND type, comprises: Reading from the NVM predetermined reference data stored therein and being encoded with an error correction code, ECC, wherein the reading is performed when a read reference voltage of the NVM, which is used as a reference voltage, such as a threshold voltage, for the reading, is set at a defined voltage level; decoding the read data and observing a number of bit errors, e.g., in a codeword, of the read data in relation to the reference data; and defining a new voltage level of the read reference voltage for a subsequent reading of data from the NVM based on the observed number of bit errors and setting the read reference voltage to the defined new voltage level.

A semiconductor system includes a first semiconductor chip, a second semiconductor chip stacked above the first semiconductor chip, a controller configured to control the first and second semiconductor chips, a first wiring connected between the controller and each of the first and second semiconductor chips and by which a first signal is to be transmitted from the controller to each of the first and second semiconductor chips, a second wiring connected between the controller and the first semiconductor chip and by which a current of the first signal flowing through the first wiring to the first semiconductor chip is to be returned to the controller, and a third wiring connected between the controller and the second semiconductor chip and by which a current of the first signal flowing through the first wiring to the second semiconductor chip is to be returned to the controller.