Example embodiments provide for a storage device that includes a storage controller including a plurality of analog circuits and at least one nonvolatile memory device including a first region and a second region. The at least one nonvolatile memory device stores user data in the second region and stores trimming control codes in the first region as a compensation data set. The trimming control codes are configured to compensate for offsets of the plurality of analog circuits and are obtained through a wafer-level test on the storage controller. The storage controller, during a power-up sequence, reads the compensation data set from the first region of the at least one nonvolatile memory device, stores the read compensation data set therein, and adjusts the offsets of the plurality of analog circuits based on the stored compensation data set.

Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.

Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.

A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.

Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.

A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.

A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line; a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line; at least one word line leakage detection circuit, configured to detect a leakage state of the selected word line; and at least one coupling circuit corresponding to the word line leakage detection circuit. The coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit, and the isolation capacitor is used for isolating the word line leakage detection circuit and the word line driving circuit.