The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including memory cells, a peripheral circuit configured to program the memory cells in a set program state during a test operation and perform a test erase voltage application operation on the memory cells programmed in the set program state, and control logic configured to control the peripheral circuit to count abnormal memory cells of which a threshold voltage is less than a set threshold voltage among the memory cells.

In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.

Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.