A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.

The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).

Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

A method for screening bad columns in a data storage medium includes steps of: writing predetermined data into at least one sample block; comparing the written data with the predetermined data to calculate numbers of error bits in the plurality of columns; defining an inspection window covering a portion of the columns; summing the numbers of error bits in the portion of columns in the inspection window to obtain a total number of error bits and determining whether the total number of error bits is greater than a number of correctable bits; if yes, determining a start point and a terminal point of a bad column interval in the inspection window, wherein the numbers of error bits in the columns between the start point and the terminal point are greater than a threshold of error bits; and labeling the columns in the bad column interval as bad columns.

In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.

Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.