The disclosed technology provides for automatically skipping bad block(s) in continuous read or sequential read operations in memory devices including NAND flash memory. Bad blocks can be skipped by analyzing block integrity during one at a time addressing of the blocks, or by skipping sets of consecutive bad blocks in a set of bad blocks using stored bad block information. Multiple sets of consecutive bad blocks can also be analyzed and skipped. A list of good blocks can be maintained, and only good blocks are used when performing a continuous cache read or sequential read operation. The list can be maintained in non-volatile memory enabling the device to load the block addresses upon power on startup. Additionally, a command to add additional blocks when received can implement adding new blocks to the list.

The disclosed technology provides for automatically skipping bad block(s) in continuous read or sequential read operations in memory devices including NAND flash memory. Bad blocks can be skipped by analyzing block integrity during one at a time addressing of the blocks, or by skipping sets of consecutive bad blocks in a set of bad blocks using stored bad block information. Multiple sets of consecutive bad blocks can also be analyzed and skipped. A list of good blocks can be maintained, and only good blocks are used when performing a continuous cache read or sequential read operation. The list can be maintained in non-volatile memory enabling the device to load the block addresses upon power on startup. Additionally, a command to add additional blocks when received can implement adding new blocks to the list.

Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.

Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.