Embodiments of the present disclosure provide a system for testing multicore firmware (FW) in a memory system and a method thereof. A test system includes a test device and a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks. The test device generates test preconditions for the plurality of FTL cores and provides the test preconditions to the plurality of FTL cores, the test preconditions being different from each other. Each of the plurality of FTL cores performs one or more test operations based on a corresponding test precondition of the test preconditions.

The present disclosure provides a semiconductor test method. The semiconductor test method includes the operations of: receiving a source code written in an interpreted language; and performing, by a first test apparatus, a first test on a device under test (DUT) based on the source code. The operation of performing, by the first test apparatus, the first test on the DUT based on the source code includes the operations of: interpreting, by a processor, the source code to generate a first interpreted code; and performing the first test on the DUT according to the first interpreted code. The first test apparatus is configured to execute the first interpreted code written in a first language.

The present disclosure provides a semiconductor test method. The semiconductor test method includes the operations of: receiving a source code written in an interpreted language; and performing, by a first test apparatus, a first test on a device under test (DUT) based on the source code. The operation of performing, by the first test apparatus, the first test on the DUT based on the source code includes the operations of: interpreting, by a processor, the source code to generate a first interpreted code; and performing the first test on the DUT according to the first interpreted code. The first test apparatus is configured to execute the first interpreted code written in a first language.

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.

An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.