A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.

A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Provided is a storage apparatus that reduces the power needed to write corrected data back to a memory.

The storage apparatus includes a memory and a write control section. The memory stores data in units of multiple cells each representing a predetermined value. The write control section receives write-back data having a specific value in a position corresponding to at least one of the multiple cells, as well as a write-back command regarding the specific value. The write control section performs control to write the specific value only to the cell corresponding to the position indicative of the specific value in the write-back data.

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.