Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

A method of operating a controller includes randomly transmitting a first command to a non-volatile memory device upon a read request from a host; receiving first read data corresponding to the first command from the non-volatile memory device; determining whether the number of first error bits of the first read data is greater than a first reference value; determining whether the number of first error bits is greater than a second reference value, when the number of first error bits is not greater than the first reference value; storing a target wordline in a health buffer, when the number of first error bits is greater than the second reference value; periodically transmitting a second command to the non-volatile memory device; and receiving second read data corresponding to the second command from the non-volatile memory device.

The disclosed technology provides for automatically skipping bad block(s) in continuous read or sequential read operations in memory devices including NAND flash memory. Bad blocks can be skipped by analyzing block integrity during one at a time addressing of the blocks, or by skipping sets of consecutive bad blocks in a set of bad blocks using stored bad block information. Multiple sets of consecutive bad blocks can also be analyzed and skipped. A list of good blocks can be maintained, and only good blocks are used when performing a continuous cache read or sequential read operation. The list can be maintained in non-volatile memory enabling the device to load the block addresses upon power on startup. Additionally, a command to add additional blocks when received can implement adding new blocks to the list.

An electronic device includes a masking signal generation circuit configured to generate a test masking signal by receiving a fuse data during a period in which a test masking mode is executed; and a test mode signal generation circuit configured to, when a test command for executing a test in an internal circuit is input, execute the test based on the test masking signal.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

Methods, systems, and apparatuses related to a memory fault map for an accelerated neural network. An artificial neural network can be accelerated by operating memory outside of the memory's baseline operating parameters. Doing so, however, often increases the amount of faulty data locations in the memory. Through creation and use of the disclosed fault map, however, artificial neural networks can be trained more quickly and using less bandwidth, which reduces the neural networks' sensitivity to these additional faulty data locations. Hardening a neural network to these memory faults allows the neural network to operate effectively even when using memory outside of that memory's baseline operating parameters.

A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

A request is received to perform a multi-plane operation for data residing on a first plane and a second plane of a memory device. A first set of trim values is obtained from a first set of registers of the memory device. The first set of trim values corresponds to a first voltage shift for the data at the first plane. A second set of trim values is obtained from a second set of registers of the memory device. The second set of trim values corresponds to a second voltage shift for the data at the second set of trim values for the data at the second plane. The multi-plane operation is performed using at least the first set of trim values for the data at the first plane and at least the second set of trim values for the data at the second plane.