According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.

A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.

Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.

Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.