The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.

A semiconductor device may include a main circuit component and a spare circuit component including a plurality of spare elements and selected to change a function of the main circuit component, wherein each of the plurality of spare elements is configured to block a source voltage supply.

A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.

A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

A test method for a memory device including the following steps is provided. A redundancy function of the memory device is disable and a first data is written to a first memory array. The redundancy function of the memory device is enabled and a second data is written to a second memory array. The first data and the second data are complementary. A redundancy information is read from a non-volatile memory block according to a margin condition and the second memory array is read based on the redundancy information to obtain a first readout data. A first test result is generated by comparing the second data and the first readout data. The second memory array includes a part of memory cells of the first memory array and at least one redundancy memory cell.

A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

A semiconductor system includes a controller configured to output parity information that includes an expected value at which an error correction code (ECC) encoding operation has been performed on an address in a test mode of a semiconductor device and configured to receive failure information. The semiconductor system also includes the semiconductor device configured to store an internal parity generated by performing the ECC encoding operation on the address that is input in a normal mode of the semiconductor device and configured to output the failure information generated by comparing the parity information and an output parity generated from the internal parity that is stored in the semiconductor device in the test mode.