Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller.

The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

The present disclosure relates to a method for writing into a one-time programmable memory of an integrated circuit, the method comprising attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.