An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

A method for screening bad data columns in a data storage medium comprising a plurality of data columns includes: labeling or recording a plurality of bad data columns as a bad data column group, wherein the bad data columns are selected from the data columns in the data storage medium, each of the bad data column groups labels or records a position and a number of the bad data columns; determining whether the total number of the bad data columns is greater than a total number of the bad data column groups; and if yes, labeling or recording any two bad data columns of the bad data columns spaced apart by P data columns as one of the bad data column groups, wherein P is a positive integer.

Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

Provided is a memory device including a memory cell array including a normal area in which a plurality of memory cells are arranged, and a redundancy area in which a plurality of redundancy memory cells are arranged, and a repair controller configured to control a repair operation on a defect cell from among the plurality of memory cells according to a first repair unit, and switch a repair unit from the first repair unit to a second repair unit different from the first repair unit when the repair operation based on the first repair unit is completed.

A smart self-repair device and method of self-repairing a package is disclosed. The smart self-repair device may include a fuse array configured to store information regarding respective bits of a fail address in fuses. The smart self-repair device may include a self-repair control circuit configured to control repairing of not only a target mat in which a fail occurs, but also adjacent upper and lower mats sharing a sense amplifier along with the target mat, and to output fail address information corresponding to a fail mode, and row fuse set information or a column fuse set information. The smart self-repair device may include a data control circuit configured to output repair information to the fuse array based on the fail address information and the row fuse set information or the column fuse set information, and may include a control circuit configured to control a rupture operation of the fuse array.