A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.

Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.

Provided are a fuse blowing method and apparatus for a memory, a storage medium, and an electronic device. The method includes: controlling a memory to enter a test mode, and reducing an internal clock frequency of the memory (S210); starting a fuse blowing load mode, and controlling the memory to enter a fuse blowing mode (S220); enabling internal precharge of the memory, and writing a location of a fuse to be blown into a fuse blowing location register (S230); starting a fuse blowing process of the memory, and disabling the internal precharge after preset time (S240); and controlling the memory to exit the fuse blowing mode and the test mode successively (S250).

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.