A memory device includes at least one memory bank comprising a set of redundant word lines, a set of normal word lines, and row hammer refresh logic. The RHR logic comprises a first input to receive a first signal indicative of whether a match was generated at a fuse of the memory device, a second input to receive a redundant row address corresponding to a first location of a memory array of the memory device, a third input to receive a word line address corresponding to a second location of the memory array of the memory device. The RHR logic also comprises an output to transmit at least one first memory address adjacent to the first location or at least one second memory address adjacent to the second location based on a value of the first signal.

A memory device includes at least one memory bank comprising a set of redundant word lines, a set of normal word lines, and row hammer refresh logic. The RHR logic comprises a first input to receive a first signal indicative of whether a match was generated at a fuse of the memory device, a second input to receive a redundant row address corresponding to a first location of a memory array of the memory device, a third input to receive a word line address corresponding to a second location of the memory array of the memory device. The RHR logic also comprises an output to transmit at least one first memory address adjacent to the first location or at least one second memory address adjacent to the second location based on a value of the first signal.

The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.

A repair circuit includes: a plurality of redundant memory cells, each redundant memory cell being configured with a state signal; and a repair module connected to the plurality of redundant memory cells and configured to determine target memory cells from the redundant memory cells based on the state signals and repair defective memory cells through the target memory cells. The target memory cells are in one-to-one correspondence to the defective memory cells. The repair module can repair, at each of multiple repair stages, different defective memory cells, the plurality of redundant memory cells being shared at the multiple repair stages.

Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).