A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, each of which has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing address information of the main columns repaired using the plurality of spare columns. At least one of the plurality of storage units included in the spare column remap storage is provided to store address information of the main column repaired in one of the plurality of sub-arrays and address information of the main column repaired in another of the plurality of sub-arrays.

The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

In accordance with an embodiment, an electronic circuit includes at least five redundant circuit parts, which are configured to execute the same function in order to provide redundancy. The at least five redundant circuit parts are arranged in such a way that critical nodes of fewer than half of the circuit parts lie on an imaginary straight line.

A memory device including a memory cell region having a normal cell array and a redundant cell array, a fuse unit having a plurality of fuse sets corresponding to the redundant cell array and which is used for programming an address of a repair target memory cell of the normal cell array and a deciding unit which determines fuse sets that are used in a first operation mode according to a control signal.

A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.