Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

In accordance with an embodiment, an electronic circuit includes at least five redundant circuit parts, which are configured to execute the same function in order to provide redundancy. The at least five redundant circuit parts are arranged in such a way that critical nodes of fewer than half of the circuit parts lie on an imaginary straight line.

Disclosed are a stacked memory device and a method of repairing the same, in which spare cells for a post-bond test and repair process are disposed in a base die and the spare cells are used in each memory layer as many as the number desired, a repair result after the test is permanently stored, and the spare cell of the base die and the memory layer are simultaneously approached and meaningful data is selected, so that it is not necessary to newly perform a test even though power of a memory is blocked, it is possible to solve time wasted during an approach to a memory layer after a spare memory performs determination, and it is possible to secure a high repair rate.

An electrical fuse (E-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the E-fuse circuit. The E-fuse circuit comprising: a boot-up controller configured to generate at least one fuse address and a sensing enable signal, an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and configured to output fuse data including failed data if a failure has occurred in an E-fuse of the plurality of fuse sets, based on the fuse address and the sensing enable signal, a fail controller configured to detect failed data from the fuse data, and output a failed signal and a failed address storage circuit configured to store a failed address from among the fuse addresses based on the failed signal.

Disclosed are a stacked memory device and a method of repairing the same, in which spare cells for a post-bond test and repair process are disposed in a base die and the spare cells are used in each memory layer as many as the number desired, a repair result after the test is permanently stored, and the spare cell of the base die and the memory layer are simultaneously approached and meaningful data is selected, so that it is not necessary to newly perform a test even though power of a memory is blocked, it is possible to solve time wasted during an approach to a memory layer after a spare memory performs determination, and it is possible to secure a high repair rate.

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.

A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, each of which has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing address information of the main columns repaired using the plurality of spare columns. At least one of the plurality of storage units included in the spare column remap storage is provided to store address information of the main column repaired in one of the plurality of sub-arrays and address information of the main column repaired in another of the plurality of sub-arrays.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.