A method of detecting error in a data plane of a packet forwarding element that includes a plurality of physical ternary content-addressable memories (TCAMs) is provided. The method configures a first set of physical TCAMs into a first logical TCAM. The method configures a second set of physical TCAMs into a second logical TCAM. The second logical TCAM includes the same number of physical TCAMs as the first logical TCAM. The method programs the first and second logical TCAMs to store a same set of data. The method requests a search for a particular content from the first and second logical TCAMs. The method generates an error signal when the first and second logical TCAMs do not produce a same search results.

Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.

Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.

A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers. The first and second semiconductor portions are stacked vertically with one another, so that the first conductive contacts are electrically connected to the control circuit, and the first conductive contacts in combinations with the first conductive vias form a plurality of transmission channels.

Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.